| 1. | Physical units transmit information to and from the microcomputer via appropriate interface logic .
各种实体设备能够通过适当的接口逻辑电路对计算机传输（输入或输出）信息。 |
| 2. | Contains classes that extend design - time user interface logic and drawing
包含扩展设计时用户界面( ui )逻辑和绘制的类。 |
| 3. | The main research work of this thesis is as follows : ( 1 ) the design of gather and the pattern - recognition interface logic
论文的主要研究工作如下： ( 1 )采集与模式识别接口逻辑的设计。 |
| 4. | Secondly , the dissertation describes the design and implementation of communication board and the mending of the used pci interface logic
其次，本文重点讲述了对原先研制的pci接口逻辑的改进、数据通信接口板的设计与具体实现。 |
| 5. | A common architectural strategy is to layer your system , separating your user interface logic , business logic , system logic , and persistence logic from each other
通常的构造策略是将系统分层，将用户界面逻辑、商业逻辑、系统逻辑和持久性逻辑彼此分开。 |
| 6. | By using fpga and the vhdl hardware descriptive language , the interface logic between the analog signal acquisition module and the interface of sharc is designed and realized
采用fpga器件，并利用vhdl语言完成各部分逻辑接口的设计和对数据采集的控制。 |
| 7. | 2 . by using fpga and the vhdl hardwa - re descriptive language , the interface logic between the add - on bus of s5933 and the host interface of silarc is designed and realized . 3
采用fpga器件，并利用vhdl语言完成逻辑设计pci接口芯片s5933的add - on总线与sharc的hostinterface的接口逻辑。 |
| 8. | In storage portion , harddisk was selected as storage device and the ide interface logic was designed . under the controlling of state machine , integrated pio and udma timing was performed
在记录端,使用硬盘作为数据存储介质,设计了ide接口逻辑,实现了在状态机控制下的完整的pio时序和udma时序。 |
| 9. | Becausc of using the advanced dsp , popu1ar high speed pci bus and laxge scale fpga , using vhdl hardware descriptive language to design the interface logic , the level of designed hardware is to a certain degree
由于采用了先进的dsp处理芯片和结构、流行的高速总线pci总线、大规模fpga及vhdl硬件描述语言进行接口逻辑设计，使得本设计的整个系统具有相当的水平。 |
